The present disclosure relates to memory controllers and, more specifically, to a memory controller for allocation of a plurality of nonvolatile memory areas for writing of data, a storage apparatus, an information processing system, and a control method therefor.
The previous storage apparatus includes a plurality of memories for combined use aiming for better performance. In order to improve the performance, such a storage apparatus has been making an attempt to perform memory allocation differently for writing of data. That is, when the storage apparatus uses a NAND flash memory and a DRAM (Dynamic Random Access Memory), for example, the DRAM is written with very-frequently-accessed data, and the NAND flash memory is written with any other data.
This memory allocation aims to improve the performance by utilizing the characteristics of the DRAM, i.e., allowing high-speed access.
A nonvolatile memory including the above-mentioned NAND flash memory has limited rewrite cycles compared with the DRAM, and thus has a limited life as a memory. In consideration thereof, for improving the performance of the storage apparatus including a plurality of nonvolatile memories, proposed is to increase the life of the nonvolatile memories. As an example, Japanese Patent Application Laid-open No. 2011-186562 (hereinafter, referred to as Patent Document 1) describes a memory management apparatus that performs memory allocation for data writing based on information about erase cycles of memories, characteristics of data for writing, and others.